1. Field of the Invention
The present invention generally relates to a pointer register device for retaining a pointer value (i.e., an address for accessing a memory), updating the pointer value by arithmetic operation, and the like in, e.g., a processor included in a computer. More particularly, the present invention relates to a pointer register device including a register called a shadow register (back register) and a method for updating a pointer value.
2. Description of the Related Art
For example, a processor included in a computer includes registers for retaining a pointer value (i.e., an address for accessing a memory). The registers can be accessed more rapidly than the memories. Therefore, the registers are used to store a pointer value that is frequently or continuously referred to. As the processing of the processor is complicated, the number of pointer values to be stored in the registers is also increased. If the number of pointer values to be stored in the registers exceeds the number of registers that are actually included in the processor, data transfer must be frequently conducted between the registers and the memory, degrading the processing efficiency. If the number of registers is increased, the number of instructions and the instruction length are also increased. In other words, the number of instructions must be increased according to the increase in the number of registers, and the instruction length must be increased in order to specify the register in each instruction. This complicates the hardware and the circuit scale.
A known method to increase the substantial number of registers without increasing the apparent number of registers (i.e., the number of registers when viewed from the software) is to provide registers called shadow registers or back registers. In this method, the processor includes a register set (including two registers) capable of being accessed in an alternative manner, instead of a commonly used independent register. In this case, the same instruction set is used as that in the case where there is only a selected register, except that it includes an instruction to select one of the registers. The resultant processing capability is approximately the same as that obtained when the number of registers is increased. Moreover, this processing capability can be obtained without causing disadvantages like a complicated instruction set. Note that the term xe2x80x9cregister setxe2x80x9d herein refers to a set of registers that are used in an alternative manner. Therefore, the xe2x80x9cregister setxe2x80x9d is different from a xe2x80x9cregister pairxe2x80x9d, i.e., a pair of registers that are used together as a single register having a double bit length.
In a known configuration using such a register set, a base value is retained in the non-selected register and the base value plus or minus a prescribed offset value is stored in the selected register for later reference. This configuration makes good use of the two registers and enables efficient operation of the offset. Moreover, since it is only the selected register that can be directly accessed by an instruction, this configuration can be implemented without complicating the instruction set.
Hereinafter, the specific structure of a conventional pointer register device including such a register set will be described.
FIG. 6 is a circuit diagram of the structure of a conventional pointer register device.
In FIG. 6, a front/back register set 201 includes a first register 201a and a second register 201b for retaining a pointer value. The front/back register set 201 is basically recognized as a single register when viewed from the outside of the pointer register device (i.e., from a program instruction). Either the register 201a or 201b selected according to the program instruction is accessed. In other words, in reading and writing a pointer value, the registers 201a, 201b need not be distinguished from the outside. (Note that the terms xe2x80x9cfrontxe2x80x9d and xe2x80x9cbackxe2x80x9d are merely used to distinguish the selected register from the non-selected one, and are not used to fixedly distinguish between the first and second registers 201a, 201b.)
A transfer switch set 202 includes switches 202a, 202b respectively corresponding to the registers 201a, 201b. The transfer switch set 202 selects either writing the addition result of an adder 205 or a pointer value applied from the outside of the pointer register device, or transferring a pointer value between the registers 201a, 201b (i.e., writing a pointer value retained in one register to the other).
A transfer path 203 is a signal path for transferring a pointer value between the registers 201a, 201b. 
A register select switch set 204 includes a read select switch 204a and a write select switch 204b. The register select switch set 204 selects either the register 201a or 201b in order to read or write a pointer value.
The adder 205 adds a pointer value retained in the register 201a, 201b and an additional value applied from the outside of the pointer register device.
An adder select switch 206 selects either the addition result of the adder 205 or a write pointer value applied from the outside of the pointer register device for input to the front/back register set 201.
A switch control section 207 controls the respective switching states of the transfer switch set 202, the register select switch set 204 and the adder select switch 206. For example, the switch control section 207 retains information designating the register (201a or 201b) from or to which a pointer value is to be read or written, and outputs a switch signal S based on that information to switch the register selector switch set 204.
A program-instruction execution control section 208 controls operation of each part based on a program instruction. When executing a program instruction to switch to the register 201a, 201b, the program-instruction execution control section 208 instructs the switch control section 207 to switch the register select switch set 204 accordingly. Basically, when executing other program instructions including an instruction to write or read a pointer value, the program-instruction execution control section 208 will not instruct the switch control section 207 to switch the register select switch set 204. As described above, the pointer value is thus written to or read from either the register 201a or 201b that has already been selected. However, during the operations of updating a pointer value described below, the program-instruction execution control section 208 controls switching of the register select switch set 204 or the like as necessary.
Typical operations in the above pointer register device include: (A) xe2x80x9crelative-pointer updating operationxe2x80x9d; (B) xe2x80x9cbase-pointer updating operationxe2x80x9d; and (C) xe2x80x9cinitial-pointer updating operationxe2x80x9d. Hereinafter, these operations will be described specifically.
(A) Relative-Pointer Updating Operation
The relative-pointer updating operation (hereinafter, operation (A)) is the operation of replacing an original pointer value retained in the front/back register set 201 with a pointer value for actual access to a memory (i.e., an effective address). More specifically, the original pointer value retained in one register of the front/back register set 201 and a relative pointer value designated by a program instruction or the like are added, and the sum is written to that register.
Operation (A) will now be described specifically with reference to FIG. 7. It is herein assumed that an original pointer value A retained in the first register 201a is to be replaced with the sum of the original pointer value A and an additional value C, i.e., (A+C).
(0) The respective switching states of the register select switch set 204 and the transfer switch set 202 are as shown in FIG. 7 before operation (A). More specifically, the switches 204a, 204b select the first register 201a, and the switch 202a allows the sum obtained by the adder 205 to be written to the first register 201a. In this state, it is possible to output a pointer value in the first register 201a to the outside of the pointer register device according to a program instruction to access a memory. It is also possible to write an additional pointer value to the first register 201a if the adder select switch 206 is switched to select an external write pointer value.
(1) In this state, the pointer value A read from the first register 201a and the external additional value C are applied to the adder 205. The adder 205 adds the pointer value A and the value C. The sum (A+C) is then written to the first register 201a. 
The above operation is given by the following assignment statement:
X=(X; A)+C(as a result, X; (A+C))
where xe2x80x9cXxe2x80x9d is a variable indicating the first register 201a, and xe2x80x9cX; Axe2x80x9d indicates the state in which the first register 201a retains the pointer value A therein.
In the case where the first register 201a can be written and read simultaneously (e.g., in the case where the first register 201a is based on a master-slave-type flip-flop), the above operation (A) can be conducted in a single machine cycle.
Note that the same operation is conducted even when the second register 201b is selected instead of the first register 201a. In other words, xe2x80x9c201axe2x80x9d and xe2x80x9c201bxe2x80x9d are merely used to distinguish the selected register from the non-selected one. The same operation is conducted whether the register 201a or 201b is selected. The same applies to the following description.
(B) Base-Pointer Updating Operation
The base-pointer updating operation (hereinafter, operation (B)) is the operation of obtaining the sum of a pointer value (base pointer value) retained in the front/back register set 201 and a relative pointer value, as in operation (A). Operation (B) is different from operation (A) in that the sum thus obtained is stored in the other register (i.e., the register that does not retain the base pointer value). Provided that the base pointer value B is retained in one register (e.g., the second register 201b), the sum of the base pointer value B and the additional value C, (B+C), must be stored in the other register (first register 201a). This is because the base pointer value B need be stored for use in later processing. Operation (B) will now be described specifically.
(0) The respective switching states of the register select switch set 204 and the transfer switch set 202 are as shown in FIG. 8A before operation (B). More specifically, the switches 204a, 204b select the first register 201a, and the switch 202a allows the sum obtained by the adder 205 to be written to the first register 201a. 
(1) In operation (B), the switch 202a is first switched to the transfer path 203 as shown in FIG. 8B, so that the base pointer value B read from the second register 201b is written (transferred) to the first register 201a. 
(2) The switch 202a is then switched back to the adder 205. As in step (1) of operation (A) (FIG. 7), the base pointer value B thus transferred is read from the first register 201a. The adder 205 then adds the base pointer value B and the additional value C. The sum (B+C) is then written to the first register 201a. 
The above operation is given by the following assignment statement:
X=(Y; B) (as a result, X; B)
X=(X; B)+C (as a result, X; (B+C))
where xe2x80x9cXxe2x80x9d is a variable indicating the first register 201a, xe2x80x9cYxe2x80x9d is a variable indicating the second register 201b, xe2x80x9cY; Bxe2x80x9d indicates the state in which the second register 201b retains the base pointer value B therein, and xe2x80x9cX; Bxe2x80x9d indicates the state in which the first register 201a retains the base pointer value B therein.
In operation (B), the steps of reading and adding the transferred base pointer value and storing the addition result can be conducted in a single machine cycle as in operation (A). However, these steps cannot be conducted simultaneously with the step of transferring the base pointer value. Therefore, at least two machine cycles are required for operation (B).
(C) Initial-Pointer Updating Operation
The initial-pointer updating operation (hereinafter, operation (C)) is used for, e.g., loop processing (processing of sequentially accessing the elements in an array). For example, in operation (C), the pointer value B retained in the second register 201b is transferred to the first register 201a for use as a base pointer value of operation (A) in the following loop processing. In addition, the pointer value B retained in the second register 201b is replaced with the sum of the pointer value B and the additional value C, (B+C), for use as a base pointer value in the loop processing subsequent to the above following loop processing.
Operation (C) will Now be Described Specifically.
(0) The state before operation (C) is the same as that described in step (0) of operation (B) (FIG. 8A).
(1) The pointer value is transferred from the second register 201b to the first register 201a in the same manner as that described in step (1) of operation (B) (FIG. 8B).
(2) As shown in FIG. 9A, the register select switch set 204 is then switched to the second register 201b. As in step (1) of operation (A) (FIG. 7) (except that the selected register is herein the second register 201b), the pointer value B is read from the second register 201b. The adder 205 then adds the pointer value B and the additional value C. The sum (B+C) is then written to the second register 201b. As shown in FIG. 9B, the register select switch set 204 is then switched back to the first register 201a. In this way, the pointer value B retained in the second register 201b is transferred to the first register 201a for use as a base pointer value or the like. In addition, the pointer value (B+C) is retained in the second register 201b for later use.
The above operation is given by the following assignment statement:
X=(Y; B) (as a result, X; B)
Y=(Y; B)+C (as a result, Y; (B+C)).
In operation (C) as well, the steps of reading and adding the transferred pointer value and storing the addition result cannot be conducted simultaneously with the step of transferring the pointer value. Therefore, at least two machine cycles are required for operation (C).
The above conventional pointer register device requires the transfer path 203 and the transfer switch set 202 for operations (B), (C) and the like, resulting in large circuit scale.
Moreover, at least two machine cycles are required for operations (B), (C) and the like, requiring a large amount of processing overhead.
It is an object of the present invention to provide a pointer register device capable of implementing improved processing efficiency while suppressing the circuit scale and processing overhead, and a method for updating a pointer value.
In order to achieve the above object, according to a first aspect of the present invention, a pointer register device includes a register set, a read select section, a write select section, a switch control section, an adding section, and a program-instruction execution control section. The register set includes a plurality of pointer registers for retaining a pointer value. The read select section selects a pointer register from the register set in order to read a pointer value therefrom. The write select section selects a pointer register from the register set in order to write a pointer value thereto. The switch control section controls respective switching states of the read select section and the write select section. The adding section adds the pointer value read from the pointer register selected by the read select section and a prescribed additional value, and writes the sum to the pointer register selected by the write select section. The program-instruction execution control section is responsive to a program instruction, for controlling operation of writing a pointer value applied from outside of the pointer register device to a pointer register that is selected in advance before executing the program instruction, and reading a pointer value from the selected pointer register to the outside of the pointer register device. The switch control section allows the read select section and the write select section to select different pointer registers.
According to the above pointer register device, the write select section selects a pointer register different from that of the read select section. This enables the same pointer value as that read from a pointer register to be retained therein while replacing a pointer value in another pointer register with the sum obtained by the adding section. In this case, the pointer value need not be transferred between the pointer registers. As a result, various pointer operations can be conducted rapidly. Moreover, no transfer path is required between the pointer registers, whereby the circuit scale can be suppressed.
Preferably, when a prescribed program instruction is executed with a first pointer register of the register set being selected by the read select section and the write select section, the read select section first selects a second pointer register of the register set. The adding section then adds a pointer value read from the second pointer register and the prescribed additional value and writes the sum to the first pointer register. Thereafter, the read select section selects the first pointer register again.
According to the above pointer register device, for example, an effective address, i.e., the sum of a base pointer value retained in the second pointer register and a relative value, can be stored in the first pointer register without changing the base pointer value in the second pointer register. Moreover, the pointer value need not be transferred between the pointer registers. As a result, the above updating operation can be conducted at a high speed.
Preferably, when a prescribed program instruction is executed with a first pointer register of the register set being selected by the read select section and the write select section, the read select section first selects a second pointer register of the register set. The adding section then adds a pointer value read from the second pointer register and the prescribed additional value and writes the sum to the first pointer register. Thereafter, the write select section selects the second pointer register.
According to the above pointer register device, in, e.g., loop processing, the sum of the pointer value in the second register and a relative value is stored in the first pointer register for use in the following loop processing. Moreover, the read select section is switched to the second pointer register so that the pointer value in the second pointer register can be used in the loop processing subsequent to the above following loop processing. Since the pointer value need not be transferred between the pointer registers, the above updating operation can be conducted at a high speed.
According to another aspect of the present invention, a method for updating a pointer value by using the above pointer register device includes the steps of: switching the read select section to select a second pointer register of the register set from a state where the read select section and the write select section selects a first pointer register of the register set; adding a pointer value read from the second pointer register and the prescribed additional value and writing the sum to the first pointer register by using the adding section; and switching the read select section to select the first pointer register again.
According to the above method, the operation of updating a pointer value can be conducted at a high speed, as in the case of the above pointer register device.
According to still another aspect of the present invention, a method for updating a pointer value by using the above pointer register device includes the steps of: switching the read select section to select a second pointer register of the register set from a state where the read select section and the write select section selects a first pointer register of the register set; adding a pointer value read from the second pointer register and the prescribed additional value and writing the sum to the first pointer register by using the adding section; and switching the write select section to select the second pointer register.
According to the above method, the operation of updating a pointer value can be conducted at a high speed, as in the case of the above pointer register device.